1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same. More particularly, the present invention relates to a semiconductor device of which reliability is improved and a manufacturing method of the same.
2. Description of the Related Art
Recently, the request for high speed signal processing in LSI has been increasing year by year. A signal processing speed of the LSI mainly depend on operating speeds of its transistors and delay time of signal transmission in interconnections (wiring). The working speed of the transistor has been increasing by reducing its size. However, in the LSI based on a design rule of less than 0.25 micrometer, the influence of the delay of signal transmission in the interconnections has been increasing on the signal processing speed in the LSI, especially in the LSI having multilayer interconnections. Conventionally, to improve the delay of signal transmission, copper (Cu) has been substituting for aluminum (Al) as a material used for the interconnection. Also, low dielectric constant film has been substituting for silicon dioxide as a material used for an interlayer insulating film (an interlayer dielectric).
The low dielectric constant film is mainly categorized by two kinds of material groups. One group includes Si—O basis materials. Another group includes organic resin basis materials. As for the Si—O basis materials, a methylpolysiloxane film with the Si—O with methyl radicals as organic radicals and a methyl silsesquioxane (hereinafter referred to as a MSQ) film are known as insulating films. The film made from the organic resin basis materials is inferior to that made from the Si—O basis materials in its mechanical strength and dielectric characteristics. Therefore, it is difficult to integrate multilayer interconnections and obtain a high reliability by using the organic resin basis materials rather than using the Si—O basis materials. Hence, it is difficult to realize an advanced device with multilayer interconnections by using the organic resin basis materials.
Here, the conventional example will be described that the device using the MSQ film which is one of the Si—O basis materials with high mechanical strength and reliability will be described. FIG. 1 is a cross sectional view showing a conventional semiconductor device.
In FIG. 1, a first SiCN film 202 is formed as a barrier insulating film on an insulating film 201 formed on a semiconductor substrate that includes transistors. A MSQ film 213, which is one of an organo-polysiloxane film, is formed on the first SiCN film 202. A SiO2 film 204 is formed on the MSQ film 213. The trenches for the interconnections are formed through the first SiCN film 202, MSQ film 213 and the SiO2 film 204. A MSQ modified film 215 is formed in the side wall of the trench. The MSQ modified film 215 is formed by exposing the MSQ film 213 in oxygen plasma when the ashing processing is carried out to the trenches (described in Japanese Laid Open Patent Application (JP-A 2002-246383)). The MSQ modified film 215 is characterized by that the film thickness of the upper part is substantially the same as that of the lower part.
A TaN film 206 is formed as one of barrier metals on the inner surface of the trench. A Ta film 207 is formed as another barrier metal on the TaN film 206. A Cu film 208 is formed on the Ta film 207 such that the Cu film 208 fill up the trench. The interconnection is composed of the TaN film 206, the Ta film 207 and the Cu film 208. A second SiCN film 209 is formed as a barrier insulating film on the SiO2 film 204 and the interconnections. Here, the trench only for interconnection is illustrated. However, repetition to form a via on the trench and another interconnection on the via enables to form the multilayer interconnections. The trench has taper shape, the width of the upper part tends to be wider than that of the lower part. Therefore, the interval between the adjacent interconnections of the upper part is closer than that of the lower part. This causes that the electric field is concentrated at the upper part of the interconnections, which may bring about dielectric breakdown.
The MSQ modified film includes smaller amount of carbon element than the MSQ film and its composition is close to SiO2. The etching rate by buffered hydrogen fluoride of the MSQ modified film solution is faster than that of the MSQ film. Therefore, it is easy to confirm the MSQ modified film and the MSQ film by observing the SEM cross sectional view of the semiconductor device after the etching.
Next, the conventional manufacturing method of the semiconductor device will be described with reference to the drawings. FIGS. 2A to 2C and FIGS. 3A and 3B are the cross sectional views showing the procedure of the conventional manufacturing method of the semiconductor device.
Firstly, As shown in FIG. 2A, the first SiCN film 202 is formed by using the plasma CVD method on the insulating film 201 formed on the semiconductor substrate. The thickness of the first SiCN film 202 is 50 nm to 100 nm. Next, the material of the MSQ film 213 is coated and baked on the first SiCN film 202 such that the MSQ film 213 is formed with the film thickness of 150 nm to 350 nm. Then, the SiO2 film 204 with the thickness of 50 nm to 200 nm is formed by using the plasma CVD method on the MSQ film 213.
Next, as shown in FIG. 2B, an ARC (anti-reflection coating) film 212 is coated on the SiO2 film 204. Then, the photoresist mask 216 patterned by using the photolithography technique with the lower limit of 0.14-micrometer level.
After that, as shown in FIG. 2C, the dry etching processing is carried out to ARC film 212, the SiO2 film 204 and the MSQ film 213 through the photoresist mask 216 by using gas including CHF3. The dry etching is stopped at the surface of the first SiCN film 202. Next, the photoresist mask 216 is removed by oxygen plasma ashing. After that, residual is completely removed by using the organic remover with amine related material. Then, the first SiCN film 202 is etched back to be removed. As a result, the trench 220 is formed in the SiO2 film 204, the MSQ film 213 and the first SiCN film 202. In this case, the MSQ modified film 215 is formed on the side wall of the trench 220. The MSQ modified film 215 is characterized by that the film thickness of the upper part is substantially the same as that of the lower part. Here, the film thickness of the upper part and the lower part is approximately less than 10 nm.
Next, as shown in FIG. 3A, after the outgassing process and the RF etching process by using Ar ions are carried out, the TaN film 206 with the thickness of 10 nm is formed as one of barrier metals on the inner surface of the trench 220. The Ta film 207 with the thickness of 20 nm is formed as another barrier metal on the TaN film 206. After that, the Cu seed film (not shown) with the thickness of 100 nm is formed on the Ta film 207. Next, the Cu film 208 with the thickness of 600 nm is formed on the Cu seed film by using Cu metal plating. Then, the semiconductor device is annealed in a furnace in the temperature range of 200 to 400 degrees Celsius.
After that, as shown in FIG. 3B, the metals (the TaN film 206, the Ta film 207 and the Cu film 208) are removed except for those in the trench 220 by using CMP (chemical mechanical polishing) technique. Then, the second SiCN film 209 with the thickness of 50 to 100 nm is formed by using the plasma CVD method on the SiO2 film 204 and the interconnections.
The MSQ film has mechanical strength lower than SiO2 by one order of magnitude. Therefore, heavy load generated by the CMP processing and the wire bonding processing brings about the film peeling of the MSQ film 213.
The MSQ film has low dielectric breakdown voltage. Particularly, the interval between the upper parts of adjacent interconnections is shorter than that between the lower parts. This makes interlayer insulating film corresponding to the upper parts of the interconnections weak in its dielectric breakdown strength in case of using the MSQ film. Especially, in case that the SiO2 as a hard mask on the low dielectric constant film is etched by the erosion in the CMP processing, the SiCN film as a cap film is formed almost directly on the low dielectric constant film. This causes that the concentration of electric field becomes remarkably high near the boundary of the SiCN film and the low dielectric constant film. Therefore, the dielectric breakdown voltage of the interconnections is reduced and the dielectric breakdown might occur. It generates the problem of the decrease of the reliability of the semiconductor device.
In conjunction with the above description, Japanese Laid Open Patent Application JP-A 2002-246383 discloses the following a forming method of an insulating film and a manufacturing method of a semiconductor device. The forming method of an insulating film includes: preparing a solution by dissolving a first polymer and a second polymer to a solvent, each of the polymers includes mainly methylpolysiloxane and an average molecular weight of one of the polymers has more than ten times larger than that of another; and forming a coating film by coating the solution on a semiconductor substrate; and an organic silicon oxide film by thermally polymerizing the first polymer and the second polymer.
Also, Japanese Laid Open Patent Application JP-A 2003-17561 discloses the following a manufacturing method of a semiconductor device and a semiconductor device. This manufacturing method of a semiconductor device includes: forming a first isolating film made from low dielectric constant material with carbon on a semiconductor substrate; forming a low carbon concentration layer in a surface of the first insulating film by processing the surface to reduce the carbon concentration of the surface; forming a second insulating film on the low carbon concentration layer; forming a trench in the first and second insulating film for metal to be embedded; embedding the metal in the trench in the insulating films; and forming a interconnection by polishing a surface of the embedded metal.
Also, Japanese Laid Open Patent Application JP-A 2001-326222 discloses the following a semiconductor device, a semiconductor wafer and a manufacturing method of the same. This semiconductor device includes a multilayer insulating film having interconnections on a semiconductor substrate. The multilayer insulating film includes a first insulating film made from an organic lower dielectric constant material than silicon dioxide, a second insulating film made from a polysiloxane compound with Si—H group formed on the first insulating film, a third insulating film made from an inorganic material formed on the second insulating film.
Also, Japanese Laid Open Patent Application JP-A 2000-294634 discloses the following a semiconductor device and a manufacturing method of the same. This semiconductor device includes a plurality of interconnections on a substrate, wherein metals are placed between the interconnections. An inorganic insulating film is arranged at the side wall faced to adjacent interconnection.
Also, Japanese Laid Open Patent Application JP-A Heisei 11(1999)-87502 discloses the following a manufacturing method of a semiconductor device. This manufacturing method of a semiconductor device includes: forming a first insulating film on a substrate having a first interconnection layer; forming a second insulating film on the first insulating film and a third insulating film on the second insulating film, sequentially; forming a first resist pattern having an opening pattern corresponding to the a connection hole for the first interconnection on the third insulating film; transferring the pattern of the first resist pattern to the third insulating film by selectively etching the third insulating film while using the first resist pattern as a mask and the second insulating film as an anti-etching mask for the first insulating film; and removing the first resist pattern by using the second insulating film as a protect mask for the first insulating film.